1. Field of the Invention
The present invention relates to an acoustic signal processing apparatus and, more particularly, to an acoustic signal processing apparatus comprising a plurality of infinite impulse response type digital filters, which apparatus can minimize an influence of limit cycle noise generated from each digital filter.
2. Description of the Prior Art
As effector apparatuses for sound sources used in electronic musical instruments, or for the electronic musical instruments, various digital effectors, such as a digital reverberation apparatus, a digital delay apparatus, and the like are known. These apparatuses and various musical tone synthesizing apparatuses adopt many digital filters for controlling frequency characteristics of acoustic signals.
The digital filters can be basically classified to an FIR (finite impulse response) type filter having no signal feedback path, and an IIR (infinite impulse response) type filter having a feedback path. In view of obtained frequency characteristics, an IIR filter can obtain a steep characteristic curve by a relatively simple arrangement (the smaller number of arithmetic elements or the smaller number of multiplications/additions).
As an example of a system which employs many IIR filters, a digital reverberation apparatus (reverberation tone adding apparatus) is known. A typical arrangement of the reverberation tone adding apparatus is disclosed in, e.g., Japanese Patent Laid-Open No. Sho 58-14898.
The IIR filter has a feedback path, and an actual filter processes signals and coefficients having finite word lengths. Therefore, even if an input signal is decreased to zero, an output signal cannot be decreased to zero, and a continuous parasitic oscillation having a predetermined value (DC value) or a predetermined period occurs. This is a problem of a so-called limit cycle.
FIG. 13 shows a typical circuit arrangement of a primary IIR filter. The IIR filter shown in FIG. 13 comprises an adder 21, a memory 22, and a multiplier 23. The memory 22 is a delay memory having two-word storage addresses. This memory 22 is arranged such that when y(n) is written in the memory 22 at present time n, an output signal y(n-1) at immediately preceding time n-1 is read out. The immediately preceding output signal y(n-1) is multiplied with an amplitude level control coefficient b by the multiplier 23. The product is inputted to the adder 21. The adder 21 adds the input signal x(n) at time n, and the output b.multidot.y(n-1), thereby generating and outputting an output signal y(n). Thus, for an input digital signal x(n) such as amplitude data, an output signal y(n) defined by the following IIR formula, and the immediately preceding output y(n-1) are outputted: EQU y(n)=x(n)+b.multidot.y(n-1)
A case will be exemplified below wherein a word length of a digital signal to be processed by the primary IIR filter shown in FIG. 13 is represented by B. As is well known, an absolute value of a delayed output y(n-1) is converged to a dead band given by the following equation (1), or oscillates between positive and negative values: EQU .vertline.y(n-1).vertline..ltoreq.[0.5.times.2.sup.-(B-1) ]/(1-.vertline.b.vertline.)
For example, if b=+0.75 and B=4, the absolute value of y(n-1) is converged to a predetermined value 1/4; when b=-0.75 and B=4, it oscillates at an amplitude of .+-.1/4 and a frequency of f.sub.s /2.
In this manner, the IIR filter may keep outputting a predetermined value (DC value), or may oscillate at a frequency of f.sub.s /2 (f.sub.s : sampling frequency) due to the problem of a finite word length. The filter keeps outputting a limit cycle signal until an input exceeding a dead band value given by equation (1) is supplied.
FIG. 14 is a graph showing input and output signals obtained when a limit cycle of continuously outputting a DC value occurs. At time T.sub.1, an input signal SI1 is supplied, and an output signal SO1 is outputted in response thereto. Reference symbol LC10 designates a period in which the limit cycle occurs. During this interval, a predetermined DC value is kept outputted although an input is zero.
FIG. 15 is a graph showing input and output signals obtained when a periodic limit cycle occurs. At given time T.sub.2, an input signal SI2 is inputted, and an output signal SO2 is outputted in response to it. LC20 designates a period in which a limit cycle occurs. During this period, signals having a predetermined absolute value, and positive and negative signs are alternately and continuously outputted every sampling time.
In the limit cycle described above, even if an input signal is ended, a very low signal caused by the limit cycle is outputted. Therefore, this signal is equivalent to noise in an acoustic signal processing system. Even if a DC limit cycle occurs, it causes a problem of click noise or a DC level shift in the next circuit. As described above, the IIR filter may be undesirably converted to a kind of noise source due to the limit cycle.
For this reason, in a reverberation tone adding apparatus disclosed in Japanese Patent Laid-Open No. Sho 58-14898 described above, since a large number of IIR filters are connected in parallel with each other in a reverberation tone forming unit, if each filter causes a limit cycle, this results in a decrease in S/N ratio or a narrow dynamic range. On the other hand, in order to eliminate the influence of the limit cycle, a sufficiently large word length can be used. However, in this case, the scale of the arrangement is undesirably increased.